Binary ripple-type counter are well known and have been implemented utilizing CMOS technologies. However, the disadvantage of binary ripple carry type counters is that the input clock pulse must ripple through each flip-flop stage of the binary counter. A typical CMOS flip-flop propagation delay is of the order of 60 nanoseconds. Therefore, as an example, in a 24-state counter, the time required for the clock information to reach the last stage output is of the order of 1.5 microseconds. A synchronous counter would in many applications be much more desirable because the total counter clock to output propagation delay would never exceed one flip-flop propagation delay. However, for many state counters, this has not been attempted using CMOS technology because the die area required to implement a binary synchronous counter has been excessive.
Synchronous CMOS binary counters having a small number of stages have been manufactured. However, AND or NAND gates have been required to perform the look-ahead carry function that is required. However, the number of inputs required on each input NAND gate which is required for each state of the counter increases by one for each stage of the counter. Implementation of AND or NAND gates in the CMOS technology quickly becomes impractical to implement because the amount of die area required therefor multiplies rapidly as the number of inputs increases. A conventional binary counter having an AND gate at the input of each counter stage which indicates when logical "1"s are stored in previous counter stages is described in U.S. Pat. No. 3,422,254, inventor S. J. R. Lundin.